1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, but not by way of limitation, to a method and a circuit for applying gray-scale voltages with differing dynamic ranges to a source line driver in a LCD panel.
2. Description of the Related Art
Generally, an LCD driver includes a gate driver for driving gate lines (or row lines) and a source driver for driving source lines (or column lines) to drive an LCD panel. The gate driver applies a high voltage to an LCD device, and thereby thin film transistors are turned on, and then the source driver applies source drive signals for indicating pixel colors to the source lines, respectively and thereby an image is displayed on the LCD device.
FIG. 1 is a block diagram illustrating a conventional LCD device having a multi-channel single-amplifier structure.
Referring to FIG. 1, the LCD device includes a memory 100 storing display data, a source line driver 200 having a multi-channel single-amplifier structure, and an LCD panel 300 on which a plurality of pixels R1, G1, B1, R2, G2 and B2 are arranged. RGB signals are represented such that a red signal is r, a green signal is g, and a blue signal is b.
The source line driver 200 includes a multiplexer 210, a decoding unit 220, an amplification unit 230, and a demultiplexer 240. The multiplexer 210 multiplexes display data transmitted from the memory 100 in response to first control signals Dr, Dg and Db, and then transmits the multiplexed display data to the decoding unit 220. The multiplexer 210 consists of first switches 211, 212, 213, 214, 215 and 216 which are turned on/off in response to the first control signals Dr, Dg and Db.
The decoding unit 220 decodes output levels of the display data in response to a gray level. The decoded signals are amplified by the amplification unit 230 and then transmitted to the demultiplexer 240.
The demultiplexer 240 provides the amplified signals transmitted from the amplification unit 230 to source lines S_r1, S_g1, S_b1, S_r2, S_g2 and S_b2 in response to second control signals Tr, Tg and Tb. The demultiplexer 240 consists of second switches 241, 242, 243, 244, 245 and 246 which are turned on/off in response to the second control signals Tr, Tg and Tb.
One amplifier AMP1 of the amplification unit 230 is connected to three source lines S_r1, S_g1 and S_b1. That is, the source line driver 200 has a 3-channel per amplifier structure in which a single amplifier drives three source lines.
FIG. 2 is a timing diagram for signals in a source driver having the 3-channel per amplifier structure illustrated in FIG. 1.
Referring to FIG. 2, the control signals Dr, Dg and Db are sequentially enabled while a gate line Gi of pixels R1, G1, B1, R2, G2 and B2 is enabled. When the signal Dr is enabled, video signals transferred through the first switches 211 and 214 are transmitted to the demultiplexer 240 via decoders 221 and 222 and amplifiers 231 and 232. When the signal Dg is enabled, video signals transferred through the first switches 212 and 215 are transmitted to the demultiplexer 240 via the decoders 221 and 222 and the amplifiers 231 and 232. When the signal Db is enabled, video signals transferred through the first switches 213 and 216 are transmitted to the demultiplexer 240 via the decoders 221 and 222 and the amplifiers 231 and 232.
Signals Tr, Tg and Tb are sequentially enabled and then the gate line Gi is disabled. When the signal Tr is enabled, signals respectively amplified by the amplifiers 231 and 232 are transmitted to the source lines S_r1 and S_r2 through the second switches 241 and 244, respectively. When the signal Tr is disabled, the source lines S_r1 and S_r2 are floated.
When the signal Tg is enabled, the signals respectively amplified by the amplifiers 231 and 232 are transmitted to the source lines S_g1 and S_g2 through the second switches 242 and 245, respectively. When the signal Tg is disabled, the source lines S_g1 and S_g2 are floated.
When the signal Tb is enabled, the signals respectively amplified by the amplifiers 231 and 232 are transmitted to the source lines S_b1 and S_b2 through the second switches 243 and 246, respectively. When the signal Tb is disabled, the source lines S_b1 and S_b2 are floated. The point of time when the gate line Gi is disabled almost corresponds to or slightly goes in advance of the point of time when the signal Tb is disabled.
FIG. 3 is a circuit diagram illustrating parasitic capacitors between adjacent source lines. As illustrated in FIG. 3, coupling capacitors Crg, Cgb and Cbr exist between adjacent source lines S_r1, S_g1, S_b1, S_r2, S_g2 and S_b2. The source lines S_r1 and S_r2 are affected by noise due to video signals applied to the source lines S_g1, S_g2, S_b1 and S_b2 adjacent thereto during a period of time tr for which the source lines S_r1 and S_r2 are floated. The source lines S_g1 and S_g2 are affected by noise due to video signals applied to the source lines S_b1 and S_b2 adjacent thereto during a period of time tg for which the source lines S_g1 and S_g2 are floated.
Due to a difference between the period of time tr during which the source lines S_r1 and S_r2 are floated and the period of time tg during which the source lines S_g1 and S_g2 are floated, the source lines S_r1 and S_r2 and the source lines S_g1 and S_g2 have different noise aspects. That is, the number of times of coupling according to video signals transmitted to source lines adjacent to the source lines S_r1 and S_r2 during the period of time tr when the source lines S_r1 and S_r2 are floated is different from the number of times of coupling according to video signals transmitted to source lines adjacent to the source lines S_g1 and S_g2 during the period of time tg when the source lines S_g1 and S_g2 are floated, resulting in stripes on a screen caused by voltage level distortion.
Furthermore, a difference between charge sharing time of parasitic capacitors Crg, Cgb and Cbr between the source lines S_r1, S_g1, S_b1, S_r2, S_g2 and S_b2 and charge sharing time of capacitors of liquid crystal cells generates a voltage difference between video signals applied to the source lines S_r1, S_g1, S_b1, S_r2, S_g2 and S_b2 and video signals stored in the capacitors. This kick-back noise distorts video signals and varies transmissivity of liquid crystal to cause flicker.
A method of compensating the kick-back noise to remove stripes or flicker can be considered. However, it is difficult to compensate the kick-back noise because the source lines S_r1, S_g1, S_b1, S_r2, S_g2 and Sb2 have different kick-back noise components.